1. Field of the Invention
The invention relates to the fabrication of a semiconductor device, and more particularly, a method for increasing a surface area of a bottom electrode for a dynamic random access memory (DRAM).
2. Description of the Related Art
Since semiconductor technique has greatly improved in recent years, a memory with a faster speed and a higher capacity has rapidly developed. In general, there are two ways to increase the capacitance of a memory. One is to use a high dielectric constant material as a dielectric layer. For example, barium strontium titanate ((Ba, Sr)TiO.sub.3 or BST) having a dielectric constant of about 300-500 and a low thin-film leakage current widely applies to the DRAM of 4 Gbits and beyond. The other is to increase the efficient surface area of an electrode. Since platinum (Pt) has a low leakage current, a capacitor that consists of Pt and BST is widely adopted.
FIG. 1 is a schematic, cross-sectional view showing a bottom Pt electrode according to the prior art. Referring to FIG. 1, a semiconductor substrate 100 has a source/drain region 102. A silicon oxide layer 104 is formed on the substrate 100. The silicon oxide layer 104 has a polysilicon plug 106 that couples with the source/drain region 102. A bottom Pt electrode 110 is formed on the polysilicon plug 106. A titanium nitride barrier layer 108 is formed between the bottom Pt electrode 110 and the polysilicon plug 106.
Normally, the formation of the resulting structure comprises first depositing a Pt layer and then etching the Pt layer to form a bottom Pt electrode. However, Pt is a difficult material to etch. Thus, it is difficult to make Pt into different shapes such as a crown shape or a scale shape in order to increase the efficient surface area of the bottom electrode.